| 摘要 |
To form a device, with a simple structure and high working speed, to generate a specified pulse sequence, a first register 3 and a second register 4 are connected to the output 2 of an EPROM 1. The output 5 of the first register 3 is fed back to address lines of EPROM 1. The clock signal of a clock generator 7 is applied to another address line 6, and also goes to the clock connection 10 of the second register 4, and, via an inverter 12, to the clock connection 9 of the first register 3. The output signal of the EPROM 1 is thus transmitted alternately as a new address part into the first register 3, or as an information value which represents a pulse amplitude into the second register 4, so that a pulse sequence with the stored pulse amplitudes is available at output 15 of the second register 4. (Fig. 1). <IMAGE>
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