| 摘要 |
The circuit comprises a timing controlling circuit (10) providing first-fourth control signals (CLT1-CLT4) and channel number (CHNO), a code converter (20) including the cyclic permutable code (CPC) converting table, a memory (30) reading the former second CPC and its detection number from the table, a comparator (40) comparing the former and present second CPC states, a discriminator (50) providing a fifth control signal (CTL5), a counter (60) providing a sixth control signal (CTL6) and resetting the detection number data when the discriminator provides the fifth control signal and an output circuit (70) reading the channel number and the second CPC in sequence.
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