| 摘要 |
The present invention relates to two novel approaches for implementing an approximation of the Viterbi decoding algorithm using analog processing techniques which offer the potential for decoding at higher rates than currently achievable with digital processing decoders. The first approach employs at least one tapped delay means having a plurality of taps to enable the provision of the inverted and noninverted received analog channel waveform while path metric operations are performed by selectively switching between corresponding inverting and noninverting provisions of the at least one delay means according to the contents of a decision-directed digital memory. The second approach employs sample-and-hold circuits to store and update the path metrics based upon previous maximum-likelihood decisions. |
