| 摘要 |
A microprogram processor to execute high speed memory access when an operand indicates a memory is provided. This microprogram processor comprises an instruction register for holding a unit length of an instruction code, an instruction decoder for decoding an instruction code in the register, thus generating a signal dependent upon the fact that the operand indicates a register or a memory, a microcode decoder for decoding a microcode generated from a ROM depending upon the instruction code, thus generating a noncondition memory access signal and a next instruction start condition signal, and a next instruction start condition judgement decoder connected to receive both an output from the instruction code decoder and the next instruction start condition signal to judge whether or not the next instruction start is correct. The microcode decoder further generates a conditional memory access signal when the operand indicates a memory. Thus, a memory access signal generator circuit, e.g., comprised of a simple logic circuit responds to the conditional memory access signal and an output signal from the instruction code decoder to generate a memory access signal for starting memory access.
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