| 摘要 |
PURPOSE:To insert accurately an optional number of pulses by using a 1st and 2nd differentiation pulses synchronously with the leading and trailing edges of a clock pulse, respectively. CONSTITUTION:A 1st differentiating circuit 10 outputting a 1st differentiating pulse synchronously with the leading edge of a clock pulse, a 2nd differentiating circuit 12 outputting a 2nd differentiating pulse synchronously with the trailing edge of the clock pulse, a gate circuit 19 passing the 2nd differentiating pulse while receiving a gate pulse, and an OR circuit 20 outputting OR of the 1st differentiating pulse and the 2nd differentiating pulse passing the gate circuit are provided to the title circuit. When the output of a set circuit reaches a prescribed level with a pulse insertion signal, a gate pulse from a gate pulse generating circuit 16 is outputted to the gate circuit 19 for one period of the clock pulse or a frequency division pulse and one or the number of the 2nd differentiating pulses in response to the frequency division ratio fo the frequency divider is outputted from the gate circuit 19 and the pulse is inserted in the 1st differentiating pulse by the OR circuit 20, then outputted. Thus, the prescribed number of pulses are accurately inserted. |
