发明名称 DERAY CIRCUIT
摘要 PURPOSE: To obtain a delay circuit the delay time of which varies depending upon received data by incorporating a plurality of switching means in the circuit and making voltage dropping rates at nodes different from each other. CONSTITUTION: Each of a plurality of switching means is connected to a node so that the means can receive one of a plurality of different input signals and the voltage at the node drops from a prescribed threshold voltage so that an outputting means can generate a second output signal when one of the switching means is conducted by the corresponding input signal. In addition, at least one of the switching means is constructed so that the voltage dropping rate at the corresponding node can become different from that at the node connected to one of the other switching means when the switching means is conducted. For example, a delay circuit 1 incorporates a 16-bit LSSD register 2, OR gates 4, 6, 8, 10, and 12, and a drive-out circuit 13. Therefore, the delay characteristic of the delay circuit 1 can be set accurately.
申请公布号 JPH02241109(A) 申请公布日期 1990.09.25
申请号 JP19900028598 申请日期 1990.02.09
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 CHIYAARUZU KERORII EEDERUII;MAAKU JIYOOJI MAASHIYAARU;JIYON UIRIAMU MAASHIYUUZU;PATORITSUKU EDOWAADO PERII
分类号 H03K5/00;H03K5/13 主分类号 H03K5/00
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