| 摘要 |
PURPOSE: To simplify circuit configuration by executing floating point multiplication when first and second parallel pipeline multiplication paths and first and second adders are mutually connected and executing fixed point multiplication when the multiplication paths and the adders are selectively separated. CONSTITUTION: A multiplication unit is connected to an input logic device containing the first and second parallel pipeline multiplication paths 370 and 372, which are selectively connected so that they execute a corrected Booth algorithm. The two multiplication paths 370 and 372 process a low-order digit word and a high-order digit word of the first and second data words. The first and second adders 390 and 392 are connected to the second multipliers 388 of the respective paths 370 and 372. The adder 390 of the first multiplication path 370 is selectively connected to the input of the adder 390 of the second multiplication path 372 so that the output supplies carry input. Thus, circuit configuration is made simple. |
