| 摘要 |
PURPOSE:To eliminate simultaneous charging of a column line and a spare column line by a sense amplifier and to accelerate data reading at the time of selecting the spare column line by connecting only the selected spare column line to the amplifier. CONSTITUTION:When a spare storage cell column is selected in a spare storage cell array 24, a control signal SPECB becomes a logic '0' level, and a select command signal becomes a logic '1' level. A transistor(Tr) MOS 1 is turned OFF, a spare column gate 29 is turned ON, a node SA is electrically disconnected from column lines BL1-BLn, and connected to the selected spare column line RBLi. On the contrary, when a storage cell column of a storage cell array 23 is selected, a signal SPECB becomes a logic '1' level, and a select command signal becomes logical '0' level. The Tr MOS 1 is turned ON, the gate 29 is turned OFF, thereby the node SA is electrically connected to the selected line BLi, and electrically disconnected from the lines RBL1-RBLn1. |
