USER'S PRIVATE CLOCK GENERATION CIRCUIT

摘要

PURPOSE:To prevent a user's private clock from causing large synchronizing step-out by fixing the output frequency of a PLL circuit forcedly at a center frequency when a reference clock is abnormal. CONSTITUTION:An ON-signal is sent to a mode switching part 2 from an OR gate 14 according to whether a multi-vibrator 11 does not detect a change point within definite time or the multi-vibrator 13 does not detect the change point within a definite time after the ripple carry RC of a counter 12 is outputted. In the mode switching part 2, transistors Q1, Q2 are turned ON, and a relay RL is excited. Thus, an amplifier 67 outputs control voltage fu to show just the center of the output frequency area of a VCO 68. Accordingly, a user's private clock which is outputted from the VCO 68 and 1/n-frequency- divided by a frequency divider 69 becomes the frequency nearly equal to a normal value, and since it stands satisfactorily with in the receiving sensitivity of a subsequent multiplexer, a synchronous state can be maintained.