发明名称 MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <p>PURPOSE:To sufficiently reduce the parasitic capacitance between a pad and a board by providing pads for a wafer prober and a pad for a wire bonding on the periphery of an LSI chip, and cutting the pad for the wafer prober after wafer probing. CONSTITUTION:A pad 4 for a wire bonding, a pad 3 for a wafer prober having larger area than that of the pad 4, wirings 5 for connecting both the pads 3, 4 to an internal circuit are formed on the periphery of a semiconductor integrated circuit chip 1. After the pad 3 is probed, the wirings 5 for connecting the pads 3, 4 to the circuit are cut. Thus, only the pad for wire bonding of small area finally performs a function of a signal pad. Accordingly, parasitic capacitance is reduced, and a parasitic effect of parasitic capacitance of the pad after assembling is particularly reduced in a high frequency circuit.</p>
申请公布号 JPH02241046(A) 申请公布日期 1990.09.25
申请号 JP19890062694 申请日期 1989.03.15
申请人 NEC CORP 发明人 SENBA TAKASHI
分类号 G01R31/26;H01L21/60;H01L21/66 主分类号 G01R31/26
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