| 摘要 |
<p>PURPOSE:To reduce the area of a chip and to obtain an EPROM having a short access time by dividing a drain diffusing line connected with the drain region of a floating gate transistor in a row direction at each segment column, and connecting it to a bit line through a transfer gate transistor. CONSTITUTION:In a memory cell array, one row is made of a plurality of segment columns, each column has a segment column selection line 20, the drain region of a floating gate transistor of a memory cell contained in the column has a drain diffusing line 12 connected to a row direction, the lines 12 aligned in a column direction are connected to bit lines 16 through transfer gate transistors 14, and the gates of the transistors 14 aligned in the column direction are connected to the lines 20. A word line selector has a segment column selector and a segment word line selector.</p> |
