| 摘要 |
The controller comprises a MPU (10), a clock generator (20), a system bus controller (30) generating a first and second I/O selection control signals, a memory I/O controller (40) generating the third and forth I/O selection control signals, a reset circuit (50) applying reset signal to the MPU, an interrupt controller (60) applying the interrupt signal to the MPU in sequence fo priority, a VME bus controller (70) generating request and acknowledge signals for VME bus controller, a wait signal genertor (80) halting the MPU for 1 clock period when memory or I/O accessing, a NMI controller (90) enabling or disabling the NMI source with clear signal, a MMC interface circuit (100) interfacing the MPU and system user, a hardward supervisor (110) supervising transmission state of B-bus, and a B-bus interface controller (120) interfacing the system and outer data.
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