| 摘要 |
<p>A clock signal generating circuit comprises a reference oscillator (1), a frequency divider (2) for dviding clock signal of the reference oscillator into frequency-divided signals by switches (B1- B4), a pulurality of flip-flops for generating clock signals of various duty cycle using the output of the frequency divider, and a plurality of switches for selecting duty cycle from the output of the flip-flops.</p> |
