DATA PROCESSING SYSTEM INCLUDING A MAIN PROCESSOR AND A CO-PROCESSOR AND CO-PROCESSOR ERROR HANDLING LOGIC

摘要

In a data processing system including a main processor and a co-processor, a logic circuit is coupled to receive error and busy outputs of the co-processor to generate an interrupt output on co-incidence of active error and busy signals and to latch the busy signal to the main processor to ensure that the main processor will honor the interrupt before executing another co-processor instruction.