| 摘要 |
PURPOSE:To obtain a digital phase locked loop circuit with sure phase control, able to suppress jitter and wide phase lock range by inputting '1' or '0' level of an output inverted from a flip-flop, applying 1/n frequency division and 1/(n+1) frequency division alternately and applying 2/(2n+1) frequency division to the frequency of an input clock. CONSTITUTION:A phase control signal for one period of an output signal of a frequency divider circuit 2 and a signal with phase lead and lag of an output signal of the frequency divider circuit 2 in comparison with the input signal are inputted, a control signal 4 controls a FF 1 for one period of phase control to keep the output of the preceding period. Then independently of the output of the FF 1, when the phase is led, '0' is outputted and delayed by 1/(n+1) frequency division and when the phase is delayed '1' is outputted and advanced through 1/n frequency division. As the frequency division ratio of the frequency divider circuit 2, 1/n and 1/(n+1) frequency division are applied alternately except the phase control period and when the signal is retarded for the phase control period, 1/(n+1) frequency division is applied and when advanced, 1/n frequency division is applied. Thus, the phase control is ensured, jitter is suppressed and the phase lock range is widened. |
