| 摘要 |
PURPOSE:To obtain a memory cell of high reliability without increasing manhours by a method wherein a bit line is formed lower than a capacitor electrode in level, and the bit line is connected to a source or a drain through a connection conductor layer formed higher than the bit line in level. CONSTITUTION:In a DRAM of laminated type memory cell structure, a bit line 10 is formed on a first interlaminar insulating film 6 provided onto a MOSFET, and a bridge electrode 7 is formed thereon through the intermediary of a second interlaminar insulating film 8. The bridge electrode 7 connects the bit line 10 with either a source or a drain 5 of the MOSFET through the intermediary of a first bit line contact 9a formed inside the second interlaminar insulating film 8 and a second bit line contact 9b formed inside the first and the second interlaminar insulating film, 6 and 8. By this setup, a bit line contact can be made shallow, so that a semiconductor memory device of this design can be made easy in processing and improved in reliability. |
