发明名称 OUT OF SYNCHRONISM DETECTION CIRCUIT
摘要 PURPOSE:To prevent mis-decision of detection for out of synchronism from generation by obtaining a threshold level for detecting out of synchronism based on the past value being the result of integrating counts of an inputted synchronous information pulse. CONSTITUTION:A count A being the result of counting repetitively the number of synchronous information pulses SIP outputted from a Viterbi decoder 10 for a prescribed period is compared with a prescribed threshold level B, and when the count does not exceeds the threshold level B, it is discriminated to be in the synchronous state, and when the threshold level B is exceeded, it is discriminated to be in out of synchronism state. Then a binary counter 1 is provided, which counts the synchronous information pulse SIP and outputs the binary count A. Furthermore, a feedback type integration circuit 3 setting a feedback coefficient of a feedback loop feeding back to be multiplied with the stored value of the past count output counted by the counter 1 and adding the result to the input A is provided, and the output of the feedback integration circuit 3 is used as the threshold level B of the comparator 2. Thus, even when signal input/noise ratio is varied, the generation of mis-decision with respect to the pulse SIP is prevented.
申请公布号 JPH02237334(A) 申请公布日期 1990.09.19
申请号 JP19890059125 申请日期 1989.03.10
申请人 FUJITSU LTD 发明人 MIYAMOTO BUNICHI;YAMASHITA ATSUSHI
分类号 H04L7/00;H03L7/095;H04B7/212 主分类号 H04L7/00
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