| 摘要 |
PURPOSE:To improve reliability for input data by holding the input data sequentially at two buffer registers by a clock with a cycle almost equivalent to the time constant of a filter circuit, and outputting data in which coincidence is detected when coincidence detection is performed at a comparator as effective data. CONSTITUTION:A digital signal is inputted via the filter circuit 1, and is held sequentially at the buffer register 3 and the buffer register 4 cascade-connected to the buffer register 3 corresponding to the clock of constant cycle. The clock in this case is provided with the cycle almost equivalent to the time constant of the filter circuit 1. And the identity of both data held at both buffer register 3 and 4 is judged at the comparator 5. When coincidence is obtained in both data, the data in the buffer register 4 is sent out to a CPU side as the effective data by opening a gate 6. Thereby, it is possible to heighten the reliability for the input data handled by a data processor. |
