发明名称 |
PAGE TABLE WITHIN VIRTUAL MEMORY |
摘要 |
PURPOSE: To realize high speed operation by traslating the virtual address of a page table entrance without using a page table. CONSTITUTION: A page table entrance original form mechanism is provided so that known mutual reference information between a physical address and the corresponding virtual address for the page table entrance of the page table is contained for generating the physical address of the page table entrance from the virtual address of the page table entrance. Thus, a translation mechanism 111 for translating the virtual address of the page table entrance without using the page table can operated and the bypass line and the multiplexer of the translation mechanism 111 are eliminated from a critical data path between a central arithmetic processor 110 and a main storage mechanism 112. Thus, the operation speed of the central arithmetic processor 110 increases proportionally. |
申请公布号 |
JPH02236652(A) |
申请公布日期 |
1990.09.19 |
申请号 |
JP19890143963 |
申请日期 |
1989.06.06 |
申请人 |
DIGITAL EQUIP CORP <DEC> |
发明人 |
ROBAATO II SUCHIYUWAATO;TEIMOSHII II RENAADO;SHIERII TSUI CHIYAN RII |
分类号 |
G06F12/02;G06F12/06;G06F12/10 |
主分类号 |
G06F12/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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