| 摘要 |
PURPOSE: To guarantee that a bottle neck will not occur at the interface between MCU and an array by providing an n-bit scalar processor and an m×m bit processor array and containing an array support means connected to them. CONSTITUTION: This system is provided with the processor array 1, a scalar control unit (MCU) 2 and the array support unit 3. The array support unit 3 contains an edge register ME and an interface circuit 4. MCU 2 contains a 32 bits scalar processor controlling the execution of an instruction and addressing of the array 1. The output of the processor is inputted to an MCU register through a data bus with the width of 32 bits. The content of the register can be transmitted to the array through an interface circuit 4 in the array support unit or from the array. Thus, a design process when the size of the array is change can considerably be simplified and the bottle neck will not occur.
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