An improved memory cell layout (54) is formed including a trench cell (60) formed in a semiconductor substrate (58). The memory cell layout (54) includes a bitline (56) and a wordline (62) for storing and accessing charge. The charge is stored on a capacitor formed from a conductor (68), an insulating region (70) and a semiconductor substrate (58). Bitline (56) is primarily tangential to a trench cell (60), or may surround the periphery thereof. A wordline (62) overlies trench cell (60) and extends therein, and further may be formed of a width narrower than trench cell (60).
申请公布号
US4958212(A)
申请公布日期
1990.09.18
申请号
US19880292285
申请日期
1988.12.30
申请人
TEXAS INSTRUMENTS INCORPORATED
发明人
TENG, CLARENCE W.;RICHARDSON, WILLIAM F.;DOERING, ROBERT R.;SHAH, ASHWIN H.;SHEN, BING W.;BORDELON, MARK