| 摘要 |
PURPOSE:To reduce the number of terminals and to shorten the test time by adding a reset function to a frequency dividing circuit and providing a circuit for synchronizing a reset signal from a CPU with a reset signal from the frequency dividing circuit on an integrated circuit device. CONSTITUTION:A clock A outputted from an oscillation circuit 7 in the integrated circuit device 1 is divided by the frequency dividing circuit 8 and the divided clock is supplied to the CPU 5 as a system clock E through an oscillation clock signal line 9. When a reset signal is inputted from a reset input terminal 2, a reset circuit 3 receives the reset signal and outputs a reset signal B to a system clock synchronizing circuit 4 and the circuit 4 generates a frequency dividing circuit reset signal D and a CPU reset signal C based upon the signal B and the clock A and outputs the signals D, C respectively to the circuit 9 and the CPU 5 through a frequency dividing circuit reset signal line 10 and a CPU reset signal line 11. In such a constitution, the phase of the system clock at the time of inputting a reset signal can be univocally determined and the need for monitoring and synchronizing the system clock at the time of testing the integrated circuit device 1 can be eliminated. |
