| 摘要 |
PURPOSE:To make the operation of S/P conversion stable by selecting a data having a bit of the same phase of that of an S/P conversion readout pulse from n-set of data whose phases are deviated by one bit each outputted from n-set of flip-flops, and holding the data till the next readout pulse comes. CONSTITUTION:An inputted data 21 is shifted by n-set of flip-flops 121-12n, and n-set of data 23 read and whose phases are deviated by one bit each and an S/P conversion readout pulse 24 are inputted to each NAND circuit 13b of n-set of selection circuits 131-13n. Then a data of the same phase as that of the readout pulse 24 is selected among inputted data by the selection circuits 131-13n and inputted respectively to n-set of flip-flops 141-14n. Till the next readout pulse comes, the selected data is holding. Thus, the S/P conversion is attained without inverting the clock. |
