| 摘要 |
2046294 9010978 PCTABS00002 A frequency synthesizer (10) governed by a battery saving signal (20) having sleep and awake cycles (60, 62) comprises a phase locked loop and a control circuit (70) for enhancing the restart operation of the phase locked loop at the commencement of each awake cycle of the battery saving signal. More specifically, the phase locked loop includes a phase detector (26, 28) for locking the frequencies generated by a reference oscillator (12) and a voltage controlled oscillator (36) by adjusting a signal (38) in a storage device (34) used for governing the voltage controlled oscillator. During the sleep and awake cycles of the battery saving signal, the oscillators and phase detector are inhibited and enabled, respectively, in their operations. The control circuit is operative to inhibit the adjustment of the governing signal until both of the oscillators are determined to be effectively enabled at the commencement of each awake cycle of the battery saving signal to ensure the stored governing signal commences at its desired setting.
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