| 摘要 |
<p>PURPOSE:To adjust the phase deviation of a clock signal by allowing the clock signal supplied to a terminal to pass a clock skew adjusting circuit. CONSTITUTION:The clock signal supplied to a terminal 4 has the phase deviation adjusted by a clock skew adjusting circuit 1 and is supplied to an FF 3 through a clock distributing circuit 2. In the clock skew adjusting circuit 1, data set to a two-bit shift register 21 is decoded by a decoder 22, and as the result, one of wirings 35, 36, 37, and 38 goes to logical '1', and one of gate circuits 31, 32, 33, and 34 which are set to gate signal propagation times different from one another to obtain a desired signal propagation time difference is selected, and the clock signal supplied to a terminal 24 passes this gate circuit to adjust the phase deviation of the clock signal, and thereafter, the clock signal is outputted from a terminal 28.</p> |
