| 摘要 |
PURPOSE:To increase the computing speed by using a 3rd arithmetic circuit which produces a carry bit and a multiplexer which selects the subtraction output of a 1st or 2nd arithmetic circuit. CONSTITUTION:A carry production circuit Z serves as a 3rd arithmetic circuit and a multiplexer M4 selects the output of an adder Y1 or Y2 in accordance with the value of a carry bit RC outputted from the circuit Z and inputs the selected output to an inverter 2. At subtraction the circuit Z produces a pre scribed carry bit RC in response to the values of mantissas A and B to be computed in order to obtain the correct result of subtraction. The multiplexer M4 selects the subtraction outputs of both address Y1 and Y2 based on the bit RC. Then the circuit Z produces a rounding bit to be added to the result of a subtraction (A-B) with an addition or an arithmetic. As a result, the bit length is shortened and the computing speed of the arithmetic circuit is im proved. |
