发明名称 REDUCED STRESS PACKAGE AND ITS METHOP
摘要 PURPOSE: To reduce mechanical stress caused by shrinkage in sealing plastic material and imposed on a semiconductor integrated circuit die by a method wherein a silicon integrated circuit die is mounted on the surface of a stress reducing pad which is located apart from a die mounting pad, and the surface of the stress reducing pad is made to have a part which extends beyond the sides of the integrated circuit die. CONSTITUTION: In a package 10, a layer 22 of silicon or other materials whose thermal expansion coefficient is identical with that of silicon of a die 12 is arranged between a copper die mounting pad 18 and the silicon die 12. The silicon die 12 is so arranged on the silicon layer 22 as to enable the silicon layer 22 to extend equally beyond the die 12 on its both sides as to both an X axis and a Y axis. Both the silicon layer 22 and the silicon die 12 are mounted on a die mounting pad 18 through the intermediary of conductive polyimide resin layers 24 and 26. By this setup, mechanical stress imposed on the semiconductor die by plastic sealing material can be lessened.
申请公布号 JPH02231748(A) 申请公布日期 1990.09.13
申请号 JP19900001627 申请日期 1990.01.10
申请人 NATL SEMICONDUCTOR CORP <NS> 发明人 JIEFURII SHII DEMIN;RAHENDORA DEI PENSE
分类号 H01L23/12;H01L23/28;H01L23/495 主分类号 H01L23/12
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