发明名称 CONTROL STORAGE LOADING MEMORY FOR DATA PROCESSOR
摘要 PURPOSE:To load the control storage at a high speed and at the same time to decrease the packing pins by writing repetitively the contents of a control storage loading register and storing the control information in a control storage. CONSTITUTION:A word of a microprogram to be stored is received as a shift-in data 300, and a scan path clock 500 exclusive for loading control storage is continuously received until one word of the microprogram is applied to a control storage loading register 4. Then the contents of the register 4 are written into a control storage 1 via a control storage writing path 700. Hereafter the words of the microprogram are applied one by one into the register 4 and the contents of this register 4 are repetitively written into the storage 1. Thus all microprograms are stored in the storage 1. As a result, the storage 1 is loaded at a high speed and at the same time the number of packing pins can be decreased for a data processor.
申请公布号 JPH02231632(A) 申请公布日期 1990.09.13
申请号 JP19890053454 申请日期 1989.03.06
申请人 NEC CORP 发明人 ISHIDA YASUHIRO
分类号 G06F9/24;G01R31/3185;G06F9/445;G06F11/267 主分类号 G06F9/24
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