| 摘要 |
The generator provides the control signal corresponding to the mode of converter converting serial data to parallel one and vise versa. The generator includes a load signal generator (50) providing load signal sunchronised with clock signal of a counter (40), a counter (70) counting clock signal added with the load signal and the inversed clock signal, and a byte pulse generator (80) providing byte clock signal which is a delayed output of the counter (70). The load signal generator comprises D type flipflops (51,52) latching the data, and an AND gate (53) combining the latched data.
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