A watchdog timer works in concert with special computer program features to monitor program execution and reset the computer in case of malfunction. The computer CPU is programmed to periodically output one of an alternating pair of values to a register which holds the value for a comparator. The output value is compared to a predetermined value equal to one of the alternating output value. When the compared values are equal, the comparator outputs a reset signal to a counter. The counter counts clock pulses and if it counts to its full capacity before being reset by the comparator output, it outputs a reset signal which causes the computer to restart program execution. A second comparator may be provided to compare the alternating values to a reference value equal to the other values. Thus the comparators check for proper output of both signals and reset the counter only in response to receipt of both values. In addition a second counting system may be provided so that the computer will be reset whether the period of alternating value output increases or decreases.
