发明名称 PARALLEL PROCESSING COMPUTER SYSTEM
摘要 PURPOSE: To shorten the waiting time of message passage and to extend channel band width among nodes by providing a router means which is connected with a processing means and which route-designates information among the nodes. CONSTITUTION: It is assumed data is to be communicated from a node 4 (address 100) to a node (address 001). The exclusive OR of the addresses 100 and 001 is carried out, a relative address becomes 101 and data is route-designated from the serializer of the node 4 to the channel '0' route designation element of the node 5. Then, data is route-designated from the channel '0' route designation element of the node 5 to the channel '2' route designation element of the node 1 through a channel 2. During the process, a clock signal is generated by the serializer of the node 4 and it is received by the channel '2' route designation element of the node 1. Thus, the message passage waiting time is shortened, inter-node band width is enlarged and performance improves.
申请公布号 JPH02228762(A) 申请公布日期 1990.09.11
申请号 JP19900007267 申请日期 1990.01.18
申请人 INTEL CORP 发明人 SUTEIIBUN EFU NUUJIENTO
分类号 G06F15/16;G06F15/173;G06F15/177;H04L12/56 主分类号 G06F15/16
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