| 摘要 |
A bus interconnecting a plurality of digital modules is divided into sections interconnected by buffers so that the loading on the drive circuits of the modules is reduced. Unidirectional buffers can be used where a bus section is connected only to modules driving the bus section or only to modules receiving signals from the bus section. A bidirectional buffer is clocked so that it is only capable of signal transmission in either direction during a clock pluse, thereby eliminating the regenerative feedback which would cause the buffer to hold a signal value. The logical sense of signals used by the bus sections may all be the same or some sections may use signals of the opposite logical sense; inverting and non-inverting buffers are used as required. A gated buffer may be provided enabling signal transmission from one bus section to another to be blocked. The modules, bus and buffers may be formed as an integrated circuit.
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