A/D-omvandlare av flash-typ

摘要

A flash analog-to-digital converter includes 2N comparator circuits for an N bit resolution. Each comparator comprises a summing capacitor which is alternately connected to a reference ladder and to the input signal. The majority of the capacitors are substantially charged and discharged between input potential and reference potential each cycle. The charging/discharging tends to load both the reference ladder and the input signal source. The loading is reduced by including a D.C. biased FET between the input signal source and each summing capacitor. The FET's are biased to condition them to operate as source-followers with the summing capacitors as the load element for at least a portion of the input signal range. Respective ones of the summing capacitors are thereby precluded from charging/discharging over the full input signal excursion which in turn reduces loading on associated circuitry.