发明名称 PROGRAMMABLE LOGIC DEVICE
摘要 PURPOSE: To improve performance by removing an erasable and programmable read only memory(EPROM) cell from a signal path going from the input terminal to the output terminal of a memory array. CONSTITUTION: Plural EPROM cells 27a for storing a program and plural buffers 37 and 38 for buffering the input terminals I0 and I1 are provided, and the EPROM cell 27a is removed from the signal path of the device. Thus, each EPROM cells 27a perform enabling or disenabling of the respective buffers 37 and 38 before input signals are supplied to the input terminals I0 and I1 of the memory array 10. Since the EPROM cell 27a is accessed before the input signal is supplied, the processing speed is enhanced.
申请公布号 JPH02226811(A) 申请公布日期 1990.09.10
申请号 JP19890329789 申请日期 1989.12.21
申请人 INTEL CORP 发明人 GUREGORI DABURIYU REEDENBATSUH;MAIKERU JIEI AREN
分类号 G06F7/00;G11C16/04;G11C17/00;H03K19/177 主分类号 G06F7/00
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