| 摘要 |
<p>PURPOSE: To prevent the accumulation of clock skew errors by compensating timing skew so as to make cycles symmetrical (equal interval) with each other. CONSTITUTION: Clock distribution on respective boards (circuit boards) 52, 70A and 70B is performed by a phase locked loop(PLL) circuit 72 and a gate array (SCR) tar distribution 74 and the PLL circuit 72 is laid out uniformly on all the boards of a system. The PLL moves and controls the transition point of clock signals inputted to the gate array so as to be matched with reference clock signals, matches gate array output with the reference and obtains frequency multiple clock signals for which the skew errors are small and symmetry between the cycles is improved. Thus, the storage of the clock skew errors is prevented.</p> |
