| 摘要 |
<p>A data expansion circuit (30) for expanding data comprising a sign bit, a segment defined by n bits and an interval defined by m bits, said circuit comprising: input means (32) for receiving said data; segment decoder means (66) for decoding said segment and to thereby generate signals in dependence thereon; logic array means (52) for generating an expanded data sequence comprising the m interval bits at a first bit position according to a data expansion law and in dependence on said signals from the segment decoder; determining means for determining if said expanded data is negative; data inversion means (120) for generating the inverse of negative expanded data; output means for outputting said expanded data sequence; characterized by said logic array means (52) further comprising: inverting means (150, 152, 154) for generating the inverse of said sign bit; and introduction means for introducing the inverted sign bit at a second bit position less significant than said first bit position to thereby generate the resulting expanded data sequence. A method for expanding data comprising a sign bit, a segment defined by n bits and an interval defined m bits is also disclosed.</p> |
