发明名称 BIT SLIP CONTROL CIRCUIT
摘要 <p>PURPOSE:To control bit slip with simple circuit constitution by resetting a write counter first when a power source is applied, and next, resetting a readout counter via a reset signal delay circuit to supply a phase difference not generating the bit slip. CONSTITUTION:Since a reset signal when the power source is applied is supplied to the write counter 2 and the readout counter 3 as the phase difference of the reset signal delay circuit 4, namely, since the reset signal is supplied to the readout counter 3 via the reset signal delay circuit 4, a constant delay quantity can be supplied between a write phase and a readout phase on a memory 1. Furthermore, the delay quantity is set at a range where the difference between the write phase and the readout phase on the memory generates no bit slip. The readout counter 3 is reset by the reset signal on which the delay quantity is set, and the write counter 2 is reset by the reset signal on which no delay quantity is set. Thereby, the bit slip can be controlled with simple constitution.</p>
申请公布号 JPH02223246(A) 申请公布日期 1990.09.05
申请号 JP19890044247 申请日期 1989.02.23
申请人 NEC CORP 发明人 OKI TAIJI
分类号 H04L7/00 主分类号 H04L7/00
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