| 摘要 |
PURPOSE:To shorten the useless computing time which is caused when an overflow occurs by discontinuing a division operation at the time point when the overflow is detected in a repeating arithmetic state where the quotient is calculated. CONSTITUTION:When a 1st overflow is detected, the divisor shifted to the left by 16 bits is subtracted from the dividend to obtain the result of this subtraction equal to 0 or no borrow is produced. Under such conditions, a control circuit 5 decides that the division has an overflow. This case is the same as a conventional algorithm. When a 2nd overflow is detected, the codes of the divisor and the dividend are held by a quotient calculation circuit 3 and an arithmetic unit 1 performs a subtraction to calculate the highest bit of the quotient. When the highest bit of the calculated quatient is equal to 1 and both the dividend and the divisor have the same codes, the circuit 5 decides that the division has an overflow and thereafter the division operation is discontinued. |
