发明名称 KIISHINGOCHOSEISOCHI
摘要 PURPOSE:To control the timing of an edge part at an optional value, by detecting the front and rear edges of a digital key signal and enlarging or compressing of the data of each detection by a prescribed degree based on an indication. CONSTITUTION:A digital key KEY is supplied to a shifting/rough control circuit 38 and then fed to a fine control circuit 39. These circuits 38 and 39 are controlled by a control logical circuit 40 which receives the supply of the data and the control signal from a microprocessor. Then the front and rear edges of the signal KEY are enlarged and compressed at every sampling period and by the outputs of the RAM42-44 that prescribe the degree of enlargement and compression of the edge of the circuit 38 and a level comparator 45 that detects the front and rear edges of the signal KEY. Then the signal received a rough control is fed to the circuit 39 including a buffer memory 57 plus RAM58 and 59. Thus both edges are enlarged or compressed within a clock period.
申请公布号 JPH0239153(B2) 申请公布日期 1990.09.04
申请号 JP19810107421 申请日期 1981.07.09
申请人 SONY CORP 发明人 YAMAMOTO YOSHIKAZU
分类号 H04N5/272;H04N5/275;H04N9/74;H04N9/75 主分类号 H04N5/272
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