发明名称 MULTI-LAYER SIMULTANEOUS WIRING SYSTEM
摘要 PURPOSE:To improve the wiring accuracy by preparing a wiring layer including >=3 layers having different pattern running directions and performing the calculation of the congestion degree of each layer, the calculation of the using score of each layer, and the production of a wiring pattern respectively for each wiring subject section. CONSTITUTION:A wiring pattern is automatically decided based on the limit information on the wiring as well as a wiring subject section including of the start and target points of a circuit consisting of a multi-layer wiring layer containing plural wiring layers of different pattern running directions. In this case, the coordinates of the start and target points of a wiring pattern forming a wiring subject section and the wiring limit conditions are read out of a design information file 22 and inputted to a computer 21 in a wiring subject section extracting step S1. The congestion degree of each layer is calculated in a congestion degree calculating step S2, and the using score is calculated for each layer in a score calculating step S3. Then a wiring pattern is produced in a wiring pattern producing step S4 and then a wiring pattern is decided S5.
申请公布号 JPH02222072(A) 申请公布日期 1990.09.04
申请号 JP19890041864 申请日期 1989.02.23
申请人 HITACHI LTD 发明人 OKUMURA YORIKO;KUSUHARA JIRO;IIJIMA KAZUHIKO;FUJIWARA YASUYUKI
分类号 H01L21/3205;G06F17/50;H01L21/82;H01L23/52;H05K3/00;H05K3/46 主分类号 H01L21/3205
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