发明名称 Semiconductor memory with p-channel load transistor
摘要 A p-channel MOS transistor is connected in series to a floating gate n-channel MOS transistor forming a memory cell, so that the p-channel MOS transistor functions as the load of the memory cell. The operational characteristic of the p-channel MOS transistor determines the data-writing current of the memory cell. Hence, hardly any change occurs in the data-writing current, even if the operation characteristic of the memory cell changes. A semiconductor memory includes memory cells constituted by floating gate n-channel MOS transistors. The memory further includes a data-reading, column-selecting circuit comprising n-channel MOS transistors, and a data-writing, column-selecting circuit comprising p-channel MOS transistors. By way of the above structure, the data-writing voltage can be prevented from being lowered.
申请公布号 US4954991(A) 申请公布日期 1990.09.04
申请号 US19890447391 申请日期 1989.12.07
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SAEKI, YUKIHIRO;NAKAMURA, TOSHIMASA
分类号 G11C16/04 主分类号 G11C16/04
代理机构 代理人
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