| 摘要 |
<p>PURPOSE:To simplify a circuit by phase-matching reception serial data with a serial clock and generating the serial clock from the control signal of a counter clear means and a coincidence signal from a comparison means. CONSTITUTION:When the signal level of reception serial data changes, the content of a counter circuit 2 is captured and stored. The coincidence signal 10a of a capture comparison register 10 having a comparison function with the counter circuit 2, and the coincidence signals 11a and 12a of conveyor registers 11 and 12 having the comparison function with the counter circuit 2 which can set an optional comparison value by software clear the counter circuit 2 in a counter clear circuit 3 and change the period of the serial clock. Thus, the phase of the serial clock and reception serial data are matched. Consequently, the serial clock corresponding to an optional serial transfer speed can be generated from the count clock of a fixed frequency.</p> |
