| 摘要 |
A bipolar/CMOS decoder circuit for providing a decoded output signal includes a plurality of pull-up gate circuits (14a) and a pull-down circuit (16). Each of the gate circuite (14a) is formed of a pull-up P-channel MOS transistor (P1), a pull-down N-Channel MOS transistor (N1), and a pull-up bipolar transistor (Q1). The pull-down circuit (16) is formed of a single pull-down current source, N-channel MOS transistor (NO). The bipolar transistors and CMOS transistors are merged in a common semiconductor substrate in order to form the decoder circuit which has a high noise margin and low pattern sensitivity even with a large number of inputs.
|
