| 摘要 |
PURPOSE:To control the load power with a simple structure by outputting clock signals with the increased clock interval for higher-order bits in response to aligned positions of bits of drive control signals outputted from signal converting means. CONSTITUTION:Levels of drive control signals P1-Pn outputted from signal converting means C1-Cn are switched in response to the logic state of each bit of control data D1-Dn. The period when the level is maintained in the drive control signals P1-Pn is determined by the clock interval from a clock signal generating means 12, and it is increased for higher-order bits. The drive control signal can be set to the desired duty factor in the preset period by changing the control data D1-Dn. The consumed power of loads R1-Rn driven by the drive control signals D1-Dn can be controlled by pulse width modulation. |
