发明名称 ONSEIDEETAROKUONSAISEIHOSHIKI
摘要 <p>PURPOSE:To read out a series of data at a high speed by providing a control memory which produces an address for sound record/reproduction to be stored in a voice data memory and an address selecting ciircuit. CONSTITUTION:In a reproduction mode a microprocessor muP sets a head address A corresponding to a message, end address B and a working address C on a control memory CM. When no coincidence is obtained between address C and B compared by a comparator COM, i.e., the message is under transmission, the working address data is replaced by +1 to prepre for the next reading. Thus the output of an adder ADD is used as the input of the memory CM. While the output of a register 2 holding the address A is used as the input of the memory CM when the coincidence is obtained between addresses C and B, i.e., the message is completely transmitted.</p>
申请公布号 JPH0237639(B2) 申请公布日期 1990.08.27
申请号 JP19820223163 申请日期 1982.12.20
申请人 FUJITSU LTD 发明人 MURAYAMA MASAMI;TAKECHI HIROAKI;KUNIGAMI TOSHIO
分类号 G06F3/16;G10L13/04;G11C7/00;G11C27/00 主分类号 G06F3/16
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