| 摘要 |
PURPOSE:To efficiently compress a video signal by obtaining an interpolation block of a block not extracted with respect to a picture element position and applying orthogonal transformation coding to the sum or difference between the block not extracted and the interpolation block. CONSTITUTION:A division circuit 2 divides an input signal into plural blocks in which they have respectively a matrix picture element arrangement and then divides the plural blocks into optional blocks X and Y. Then an interpolation circuit 3 obtains an interpolation block YX from the block X with respect to the picture element position of the block Y, an adder circuit 4 obtains an arithmetic block Z being the sum of the block Y and the interpolation YX, and an orthogonal transformation coding circuit 5 applies compression processing to the block X and the arithmetic block Z through orthogonal transformation coding. Thus, an object picture number is not increased even in a video signal of nonmatrix state picture element arrangement, the sum and difference of each block form a matrix state picture element arrangement respectively and the compression of the video signal by efficient orthogonal transformation coding is attained. |
