发明名称 PHASE COMPARATOR CIRCUIT USING PHASE LOCKED LOOP
摘要 PURPOSE:To obtain an always stable sample clock output by using a VCO with high stability and slow tracking performance when the control voltage fluctuation of the VCO due to the input frequency fluctuation is small and using a VCO with low stability and high tracking performance when the control voltage fluctuation of the VCO due to the input frequency fluctuation is large so as to compare the phase. CONSTITUTION:When the fluctuation of a frequency 2fac is small, a 1st phase locked loop comprising of a phase comparator 1, a loop filter 2 and a VCO 4 applies the phase comparison. When the input frequency fac is largely fluctuated in the operation in the 1st phase locked loop, a voltage proportional to the deviated phase is generated from the phase comparator 1 and appears at a point A through a loop filter 2. When a voltage at the point A reaches a prescribed threshold level or over, a changeover switch 6 is switched and phase comparison is applied by a loop through the VCO 5. Although the stability of the VCO 5 is low in the loop, since the tracking performance is fast, the loop well tracks even a large voltage change, the phase deviation is converged and the voltage is below the threshold level.
申请公布号 JPH02213224(A) 申请公布日期 1990.08.24
申请号 JP19890033089 申请日期 1989.02.13
申请人 FUJITSU LTD 发明人 UMEZAKI YASUSHI
分类号 H04N5/06;H03L7/10;H04N19/00;H04N19/102;H04N19/134;H04N19/196;H04N19/59;H04N19/82;(IPC1-7):H03L7/10;H04N7/13 主分类号 H04N5/06
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