发明名称 SEMICONDCUTOR MEMORY DEVICE HAVING TEST PATTERN GENERATING CIRCUIT
摘要 The semiconductor memory device comprises an internal circuit including a memory circuit (32), a test pattern generator (10) and a device for receiving external signals supplied from the outside. An input switching circuit (20) is connected between the test pattern generator and the receiver for switching the input supplied to the internal circuit between output signal generated from the test pattern generator and the estimated signals. The output signals generated from the test pattern generator are input to the internal circuit through the input switching circuit in a test mode. The external signals are input to the internal circuit through the input switching circuit in a usual mode. The test pattern generator, the input switching circuit and the internal circuit are provided on the same chip.
申请公布号 KR900006163(B1) 申请公布日期 1990.08.24
申请号 KR19860006722 申请日期 1986.08.14
申请人 FUJITSU CO., LTD. 发明人 DATEMATSU DAKEOH
分类号 G11C29/00;G11C29/06;G11C29/36;(IPC1-7):G11C29/00 主分类号 G11C29/00
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