| 摘要 |
The semiconductor memory device in the form of a shift register is supplied with two-phase clock signals. One of the twophase clock signal lines (91,92) is connected to even order shift register elements (1,3,...) of the shift register, and the order of the two- phase clock signal line is connected to odd order shift register elements (2,4,...) of the shift register. Each of the shift register elements includes an output node. a gate (106,206) connected between the output node and a clock signal supplying node, a charge-up circuit (104-105, 204-205) responsive to the output signal of the proceeding shift register element for preliminarily charging a control node of the gate, and a discharge circuit (103,203) responsive to the output of the succeeding shift register element for releasing the charge of the control node of the gate.
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