发明名称 INTERFACE CIRCUIT AND CLOCK OUTPUTTING METHOD THEREOF, DATA PROCESSING CIRCUIT AND SYSTEM, AND INTEGRATED CIRCUIT
摘要 An interface circuit and a method for outputting its clock, a data processing circuit and system, and an integrating circuit are provided to reduce the size of each circuit and a cost and reliably process data of a rear stage. An AND gate(302) outputs data DI as data SDI in response to a level of a control signal CE. A logic circuit(304) outputs a clock CL as a clock SCL in response to the level of the control signal CE. An inverter(306) outputs an inverse clock /CL of the clock CL. An AND gate(308) outputs the inverse clock /CL as a latch clock LCL in response to the level of the control signal CE. A latch circuit(310) latches a voltage 'V' which becomes 'H' in response to the level of the latch clock LCL, and outputs data SCLEN. When the control signal CE is 'L', the latch circuit(310) is reset to output the data SCLEN of 'L'. An AND gate(312) outputs the clock CL as a clock SCL in response to the level of the control signal CE and a level of the data SCLEN.
申请公布号 KR20050028892(A) 申请公布日期 2005.03.23
申请号 KR20040074995 申请日期 2004.09.20
申请人 SANYO ELECTRIC CO., LTD. 发明人 ARAI, HIROYUKI;HIBINO, TAKESHI;KIMURA, TAKESHI;MOTEGI, SHUJI;TOKUNAGA, TETSUYA
分类号 H04L7/04;G06F1/04;H04L7/00;H04L12/02;H04L12/40;(IPC1-7):H04L7/00 主分类号 H04L7/04
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